1. Field of the Invention
This invention relates to analog-to-digital converters of the parallel type.
2. Description of the Prior Art
A conventional parallel analog-to-digital (A/D) converter compares an analog input signal to a set of discrete voltage levels which define voltage intervals. The converter produces a digital output indicative of the voltage interval into which the analog input signal falls. A separate voltage comparator is associated with each reference level to compare the analog input to that level. Hence, for an n bit digital code which can indicate any of 2.sup.n voltage intervals defined by 2.sup.n -1 quantum levels, 2.sup.n -1 comparators are required.
Another type of parallel A/D converter is shown in U.S. Pat. No. 4,270,118, issued to A. P. Brokaw on May 26, 1981. In that converter, the analog input is compared to 2.sup.n -1 discrete reference levels in n comparators. Each comparator produces a one-bit binary output the value of which alternates as the analog input signal increases through the discrete reference signal levels. Logic circuitry produces an n-bit code from the comparator outputs.
This type of converter can be said to have a "bit slice" architecture. As illustrated schematically in FIG. 1, the input signal in such a converter is applied in parallel to a collection of "sub-converters" each of which creates only a single bit of output representing a particular digit in the output word. FIG. 1 shows symbolically that the output of each of these sub-converters is a periodic function of the input signal with the output toggling back and forth between logic 1 and logic 0 as the input signal is increased from zero to full-scale. The sub-converter for the LSB, for example, must have the smallest "period", that is, the greatest number of 0/1 and 1/0 transitions over the full range. The next highest bit unit will have a "period" which is twice as great as the LSB's "period", and so forth.
Compared to the usual A/D converters, this "bit-slice" type of converter has several distinct advantages. It provides a true "parallel process", in that low-order bit decisions do not have to wait for high-order bits to finish conversion, as in successive approximation or cascaded schemes. Furthermore, high speed is not bought at the cost of extreme replication as in flash converters because only one "sub-converter" is required per bit.
Each bit decision is made without any information on what the state of the other output bits will be. This can lead to large errors if a standard binary-weighted output code is used. To overcome this problem, the standard binary code is replaced with a cyclic or Gray code in which sequential values differ in only one digit. In that way, only one of the "sub-converters" is ever near its threshold for any input, and small errors in the threshold can only result in an error equivalent to the smallest converter increment.
FIG. 2 lists four bits of the Gray code best suited for an A/D converter output. It is not a weighted code; i.e., each position in the code does not correspond to a particular quantity. However, it is a relatively simple matter to convert this code to a standard binary representation. Also, the regularity of the transitions is advantageous for the A/D converter disclosed herein, as will be apparent from the subsequent description.
In the interest of simplicity, the first bit of the Gray code, the bit that toggles least frequently over the input range, will be referred to as the "MSB" even though it is not the "most significant" in any sense. Similarly, "LSB" will refer to the bit that toggles most frequently.